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Qualcomm Technologies International

Qualcomm Technologies International

Chip Implementation Engineer (Staff Level)

Qualcomm are recruiting for a Chip Implementation Engineer to join their Bluetooth microchip development team. We are ideally looking for an experienced engineer with specific experience in DFT, floorplanning,and Place and Root.

Based in our Cambridge office as a technical lead and key contributor on the RTL2GDS implementation of mixed signal chips with a particular focus on floorplanning, place and route, clock tree design along with physical and timing closure. Experience of synthesis and test insertion would be an advantage. In your role as a key contributor to the implementation you will have expertise of floorplanning, place and route, clock tree design along with physical and timing closure. It would be advantageous to have a working knowledge of low power design methodologies (i..e power gating), and their impact on a physical implementation flow. Successful candidates will have a track record in delivery of digital cores or chips through a final signoff.

Key Responsibilities:

  • Key contributor for physical implementation.
  • Running place and route tools and achieving timing closure.
  • Building clock trees and feeding back design changes to improve physical results.
  • Building chip level floorplans including macro placements and padrings.
  • Helping support and Develop tool flows.
  • This role reports to the Senior Manager, Chip Implementation in Cambridge.

Minimum Qualifications

  • Experience of floorplanning, place and route, clock tree design along with physical and timing closure.
  • Practical experience of the associated EDA tools.
  • Understanding of key scripting languages particularly TCL.
  • Experience of working as part of a larger team and working to project milestones and deadlines.
  • Good team worker acting as a mentor for the junior team members and working with the wider design teams to support their efforts.

Preferred Qualifications

  • Experience of at least two areas of implementation on floorplanning, place and route, clock tree design along with physical and timing closure
  • A background in running gate level simulations could also be of help Library and Macro preparations for place and route. Proficient in scripting languages (e.g. Python, Perl, TCL)
  • Knowledge of Analogue/Full Custom design tools.
  • Experience of Low Power Design methodologies especially power gating.
  • Understanding of synthesis and test tools and their impact on the flow.
  • Use of bug-tracking and revision control systems
  • Education Requirements Degree (or equivalent qualification) in maths/science/electronics

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Organisation:  Qualcomm Technologies International